CMOS technologies are known in which a silicide layer of low resistivity is used to form the gate electrodes of transistors. With these technologies there is the problem of also integrating resistive components of multi-crystal silicon (polysilicon) which may have resistivity values higher than those of the gate electrodes by one or more orders of magnitude.
In particular, this problem arises when, together with logic functions with high switching speed (devices operating at frequencies of the order of several tens of MHz or more), it is necessary also to integrate analog functions which often require multi-crystal silicon resistors with higher resistivity values (typically &gt;20-200 Ohms/square or even of the order of several KOhms/square in particular applications).
For example, in case of ADC converters in which voltage dividers are required having good linearity properties and not too demanding from the point of view of the space occupied in the layout, manufacturing of multi-crystal silicon resistors is often regarded as the best; on the other hand this technique is not applicable to processes for digital devices, where the low resistance of signal lines is an important requirement.
The technological difficulties of such integration are well understood given the process flow and the architecture of a typical CMOS process using silicide gate electrodes. As is well known, the material of the gate lines is a composite material obtained by superimposing a high-resistivity (typically 20-200 Ohms/square) multi-crystal silicon layer and a silicide layer of a metal which generally has a low resistivity value (such as tungsten silicide with a resistivity equal to approximately 5 Ohms/square). Since this composite material is shaped by a single masking step, it is currently impossible to distinguish the two layers and the resistive components which can be obtained inevitably have the low resistivity value of the composite material.
The above-mentioned difficulties are still greater where resistors of very high value (e.g., between 10 and 100 KOhms) are to be integrated. In view of the stringent linearity and accuracy requirements, these components would have to be produced through long multi-crystal silicon strips and would require considerable space in the layout. To remedy this disadvantage it is known to manufacture resistors, in addition to those normally available in a CMOS process, of multi-crystal silicon with resistivity of the order of several KOhms/square. At the present time, such high-value resistors are integrated using a specific polysilicon masking and subsequent doping step before defining the gate lines, so as to locally shield normal doping (with POCl.sub.3 or implant) and leaving such areas with the concentration of dopant previously received through a suitable ion implantation step. In this way, multi-crystal silicon strips for the gate lines with a resistivity of the order of tens of Ohms/square together with resistors strips with resistivity of the order of several KOhms/square can be obtained at the same time by the known process.
For the reasons outlined above, this process is entirely incompatible with a MOS process using a silicide layer and constitutes a limit to optimization of the design of devices in terms of both performance and dimensions.